1. Field of the Invention
This invention concerns a semiconductor mounting board.
2. Description of the Prior Art
With the progresses in integration circuit (IC) technologies in recent years, the number of input and output terminals of an IC chip is increasing. In order to accommodate for this, a flip-chip method is employed in some cases to mount an IC chip onto a printed wiring board. In this flip-chip method, the input and output terminals are positioned two-dimensionally in a lattice-like, zigzag, or other manner on the main plane of the IC chip, pads are formed at the corresponding positions on a surface of a printed wiring board formed of resin, and these components are joined by solder bumps. Since IC chip is significantly low in thermal expansion coefficient in comparison to a printed wiring board formed of resin, a shearing stress acts on solder bumps, as the joining material due to the thermal expansion coefficient difference of the two components when heat is generated during mounting or use of the IC chip. The solder bumps may thus break after temperature changes accompanying heat generation by the IC chip occur repeatedly. In one proposal, an interposer (relay substrate), having a thermal expansion coefficient intermediate of the thermal expansion coefficients of the IC chip and the printed wiring board, is interposed between the IC chip and the printed wiring board to relax the shearing stress (Japanese Published Unexamined Patent Application No. Hei 10-12990 (paragraph 0037)).